Compilation Techniques for Reconfigurable Architectures

Compilation Techniques for Reconfigurable Architectures

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The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures.3.16 we depict an algorithmic VHDL description of the loop 1 computation in the example C code in Fig. ... s1 (8 bytes) s2 (8 bytes) u (128 bytes) Threshold (8 bytes) 1 64-bit adder/sub 28 28 16 448 1 1 Divisor by 4 1 32-bit incrementer RAM 0anbsp;...

Title:Compilation Techniques for Reconfigurable Architectures
Author: João M.P. Cardoso, Pedro C. Diniz
Publisher:Springer Science & Business Media - 2011-04-02

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